The present invention relates to semiconductor memory devices, and more particularly, to electrically programmable internal power voltage generating circuits.
As the degree of integration of semiconductor memory devices has increased, the size of elements such as transistors constituting those memory devices has been reduced. Accordingly, if a voltage from an external power source is applied across such reduced size transistors without any conversion, that transistor may be subjected to the occurrence of strong electric fields and stress. This may result in an increase in defects in each of those transistors. Hence, in a highly integrated semiconductor memory device larger than sixteen megabytes, an internal power voltage generating circuit should be used which reduces the amplitude of the voltage from an external power voltage to an internal power voltage of a given amplitude suitable for the memory device. For example, when the external power voltage is approximately five volts, an internal power voltage with an amplitude of approximately four volts is used. The internal power voltage together with the external power voltage have yet to be lowered in currently available memory devices over sixteen megabytes. In order to reduce the amplitude of the external power voltage to the amplitude of the internal power voltage, an internal power voltage generating circuit is required for uniformly providing the internal power voltage within the chip.
In conventional internal power voltage generating circuits, a reference voltage generator will generate a reference voltage so that an internal power voltage of a desired amplitude can be produced. A comparator such as a differential amplifier then compares the amplitude of the internal power voltage with the reference voltage in order to control the amplitude of the internal power voltage provided to devices within the chip. A driver will then convert an external power voltage, into an internal power voltage, in response to the control of the comparator. The internal power voltage, provided at the output terminal of the driver is thus applied to each memory device on the chip connected to one input terminal of the comparator. Therefore, in each memory device, the internal power voltage produced at the output terminal of driver will be sensed by the comparator, and will be applied to each memory device on that chip which is simultaneously corrected to that input terminal of the comparator. Consequently, in each of those memory devices connected to the comparator, the amplitude of the interval voltage as lowered to a given level is then sensed by the comparator, and output voltage of the comparator is adjusted for example, to a lower amplitude in order to again control the voltage of the internal power from the devices within the chip.
So long as a voltage from an external power source is supplied to such a conventional semiconductor memory device, the internal power voltage generating circuit operates and the constant internal power voltage is provided as long as the amplitude of the voltage provided by the external power source is above a constant amplitude. It is often necessary however, to have an internal power voltage supplied to each circuit of the chip at an amplitude equal to that of the external power voltage, as for example, during a reliability test of the chip. When manufacture of the chip is completed, a "burn-in test" is usually performed by the more conscientious semiconductor manufacturers in order to detect any defects within the chip. The "burn-in test" is a test in which a high voltage in excess of a regulated external power voltage of the chip is applied to each device constituting the chip, for a long time at a high temperature in order to detect defective devices within the chips. Since the stress applied to each device constituting a chip is increased, defective chips should theoretically be easily detected. With currently available semiconductor devices however, even though the amplitude of the external voltage is raised, a voltage applied to the chip will not be raised above the internal power voltage. Therefore, an effective and reliable "burn-in test" can not be performed and a defective chip can not be easily detected; the manufacturer will consequently have a lower reliability among the semiconductor memory devices shipped to customers after being subjected to the ineffective "burn-in test."